Architecture of Digital ASICs

Understanding the desired specifications and drawing out an architecture for Digital ASICs or the Digital portion of Mixed Signal ASICs. 

Examples include Start Up and Shut Down Sequencing, Clock Domain Definitions, Optimizing Data Paths for Area and Power while Maximizing Performance, and Defining RAM shapes and sizes

DSP Mathematical Modeling

Floating-Point and Fixed-Point modeling in Python or Matlab.  These can be used for proof of concept, setting a benchmark for performance expectation, or for providing quick demonstrations.

Our DSP expertise involves Sample Rate Conversions, developing filters for any specific application (including adaptive feedback), and Digital PLLs for Clock Data Recovery and Clock Frequency Multipliers. 

These can be implemented in DSP processors through Firmware or Custom RTL. 

ASIC/FPGA Implementation

Implementation of various Digital blocks in custom RTL using Verilog or System Verilog. These include Data Paths, Control Paths, and Clocking Blocks. 

We support implementation of digital or mathematical blocks in either an in-house or an external processor through Firmware.

We can collaborate with Verification teams using UVM and System Verilog.

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